Checked fact 498415 Nov 2026Laws and rulings

The October 2023 BIS rule (88 FR 73458) defines 'total processing performance' (TPP) as 2 x 'MacTOPS' x 'bit length of the operation', aggregated over all processing units on the integrated circuit.

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The exact words it rests on

`Total processing performance' (`TPP') is 2 x `MacTOPS' x `bit length of the operation', aggregated over all processing units on the integrated circuit.

What the source said when we opened it, on 14 Nov 2026.

The source

Implementation of Additional Export Controls: Certain Advanced Computing Items (interim final rule, 88 FR 73458)
Bureau of Industry and Security (Federal Register) · 2023-10-25

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Checked by the notis newsroom on 14 Nov 2026, against the source above.

In the story

How US AI-chip export rules use a performance score and buyer headquarters 15 Nov 2026

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“The October 2023 BIS rule (88 FR 73458) defines 'total processing performance' (TPP) as 2 x 'MacTOPS' x 'bit length of the operation', aggregated over all processing units on the integrated circuit.” ai notis, checked 14 Nov 2026. Source: Implementation of Additional Export Controls: Certain Advanced Computing Items (interim final rule, 88 FR 73458) (Bureau of Industry and Security (Federal Register)). https://ainotis.com/c/4984

As a reference (APA style)

ai notis. (2026, November 14). The October 2023 BIS rule (88 FR 73458) defines 'total processing performance' (TPP) as 2 x 'MacTOPS' x 'bit length of the operation', aggregated over all processing units on the integrated circuit [Checked claim 4984]. ai notis. https://ainotis.com/c/4984

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